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Homework 5 CMPE 316
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The purpose of this homework is to design an Encryption/Decryption module using Verilog HDL. You are required to write a testbench to evaluate the functionality of your design. Finally, you should implement the design and demonstrate its functionality on FPGA.
Vigenere is a very simple method of Encryption text characters that was first introduced by Giovan Battista Bellaso in 1553. In this scheme, the plaintext (M/C), masterkey (K), and the ciphertext (C/M) are encoded using a number between 0 and 25. For example, if you want to encode letter ‘A’ with ‘B’ as the master key, you should use “00000” for ‘A’ and “00001” for B. Considering that this cipher uses the following formula for encryption and decryption:
𝑬𝒏𝒄𝒓𝒚𝒑𝒕𝒊𝒐𝒏 => 𝐶𝑖 = 𝐸𝑘(𝑀𝑖) = (𝑀𝑖 + 𝐾) 𝑚𝑜𝑑 26 𝑫𝒆𝒄𝒓𝒚𝒑𝒕𝒊𝒐𝒏 => 𝑀𝑖 = 𝐷𝑘(𝐶𝑖) = (𝐶𝑖 − 𝐾) 𝑚𝑜𝑑 26
If plaintext is ‘A’ (“00000” or 0 in decimal) and masterkey is ‘B’ (“00001” or 1 in decimal), the ciphertext should be ((0 + 1) mod 26) which is 1 (“00001”). Decryption is the same as encryption, however, you should take care of the sign bit since all values should be positive and also represented with a number between 0 and 25.
Description of Top Module: Top module of the Vigenere cipher is shown in the following figure. This component contains both the Data path and State machine properly connected.
Vigenere Top Module
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University of Maryland, Baltimore County CMPE 316
Interface:
M (Message): A 5-bit English character that should be encoded as a number between 0 and 25. (‘A’ => 0, ‘B’ => 1, ‘C’ => 2, …, ‘Z’ => 25)
K (Key): 5-bit English character which should be used as the master key. It should also be encoded as a number between 0 and 25. (‘A’ => 0, ‘B’ => 1, ‘C’ => 2, …, ‘Z’ => 25)
ENC: 1-bit active low control signal showing the operation of the cipher: ENC: 0 => Encryption
ENC: 1 => Decryption
Start: 1-bit active high control signal showing the module should start its operation. rstn: Active-low synchronous reset signal.
NOTE: As mentioned in one of the posts in Piazza regarding this homework, you may change the polarity of the reset signal from active-low to active-high if you encounter stability issues when you implement your design in FPGA.
Output:
C (Ciphertext): A 5-bit English character which is a number between 0 and 25. (‘A’ => 0, ‘B’ => 1, ‘C’ => 2, …, ‘Z’ => 25)
You need to write a state machine that controls the sequences of the operation as follow:
You design should go to the Reset state once the Reset is activated (You should consider active-low synchronous reset). Then, it waits on the Start signal to be asserted. If Start=’0’, the it stays in the Reset state, otherwise, it goes to the next state. The Done signal should be asserted for one clock cycle when the operation (either Encryption or Decryption) is finished.
Plaintext, masterkey, and the ciphertext should be registered and they should load their respective inputs using signals issued by the controller (goes from state machine to the data path)
Deliverables:
Perform the following tasks:
- Write a synthesizable Verilog HDL code representing the circuit.
- Write a testbench verifying the operation of your circuit. Your testbench should exhaustivelytest the design for all combinations of the plaintext and key.
- Perform functional simulation of your circuit and use it to debug your Verilog HDL code.
- Synthesize and implement your circuit on your FPGA board.
a. You should use Switches 0 to 4 for the M/C input, Switches 5 to 9 for the master key, and Switch 10 for the ENC control signal. For the output, LEDs 11 to 15 should be used to display the ciphertext in the binary representation.
YOU NEED TO USE START by a push button (Should be properly debounced), AND DONE SIGNAL can be an LED
- Submit video of your working FPGA design.
- Report timing, power consumption and resource utilization of your design.
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